src/top.v


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module top (
	input clk,
	input key
);

wire rstn, clk_cpu;
assign rstn = key;

clock_divider #(.N(1024 * 1024)) clkdiv (
    .clk(clk),
    .reset(!rstn),
    .clk_out(clk_cpu)
);

cpu cpu (
  .clk(clk_cpu),
  .rstn(rstn)
);

endmodule