| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-05-14 | bug fixes | Flavian Kaufmann |
| 2024-05-13 | refactoring, runs now on fpga | Flavian Kaufmann |
| 2024-05-12 | refactoring | Flavian Kaufmann |
| 2024-05-09 | stopped initializing ram and register file to 0 at beginning | Flavian Kaufmann |
| 2024-05-08 | assemble simple rom | Flavian Kaufmann |
| 2024-05-07 | cpu | Flavian Kaufmann |
| 2024-05-05 | added memory unit | Flavian Kaufmann |
| 2024-05-05 | register file testbench | Flavian Kaufmann |
| 2024-05-05 | added register file | Flavian Kaufmann |
| 2024-05-04 | added support for multiple testbenches | Flavian Kaufmann |
| 2024-05-02 | register file | Flavian Kaufmann |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
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