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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-05 10:27:21 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-05 10:27:21 +0200 |
commit | 8d5d730269cc94fa8d5caed0e1996e3d94be25d1 (patch) | |
tree | 73154eacc2c7483a24aecd05a984638ff322d5d6 /src/register_file.v | |
parent | f6a55d5faba42120aa900e2514d9ff5d80dfca8b (diff) | |
download | riscv_cpu-8d5d730269cc94fa8d5caed0e1996e3d94be25d1.tar.gz riscv_cpu-8d5d730269cc94fa8d5caed0e1996e3d94be25d1.zip |
added register file
Diffstat (limited to 'src/register_file.v')
-rw-r--r-- | src/register_file.v | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/register_file.v b/src/register_file.v new file mode 100644 index 0000000..81bce34 --- /dev/null +++ b/src/register_file.v @@ -0,0 +1,30 @@ +module register_file #( + parameter N = 32, + parameter XLEN = 32 +)( + input clk, rst, we, + input [log2(N)-1:0] addr_rs0, addr_rs1, addr_rd2, + input [N-1:0] data_rd2, + output [N-1:0] data_rs0, data_rs1 +); + +`include "include/log2.vh" + +reg [N-1:0] registers[XLEN-1:1]; + +assign data_rs0 = (addr_rs0 == 0) ? 0 : registers[addr_rs0]; +assign data_rs1 = (addr_rs1 == 0) ? 0 : registers[addr_rs1]; + + + +integer i; +always @(posedge clk) begin + if (rst) begin + for (i = 1; i < XLEN; i = i + 1) + registers[i] <= 0; + end else if (we && (addr_rd2 != 0)) begin + registers[addr_rd2] <= data_rd2; + end +end + +endmodule |