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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-14 10:38:47 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-14 10:38:47 +0200 |
| commit | d107f7e40f02a7374b8685ba310500a6c38d43b1 (patch) | |
| tree | 55615eaface31b2473be3dae90fe822c5373f492 /src/register_file.v | |
| parent | 48b36fddef862c3cd5efbdd3ed3e86b179ac117b (diff) | |
| download | riscv_cpu-d107f7e40f02a7374b8685ba310500a6c38d43b1.tar.gz riscv_cpu-d107f7e40f02a7374b8685ba310500a6c38d43b1.zip | |
bug fixes
Diffstat (limited to 'src/register_file.v')
| -rw-r--r-- | src/register_file.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/register_file.v b/src/register_file.v index 12a0433..7f83704 100644 --- a/src/register_file.v +++ b/src/register_file.v @@ -91,7 +91,7 @@ assign rd1 = ra1 == 0 ? 32'b0 : regs[ra1]; assign rd2 = ra2 == 0 ? 32'b0 : regs[ra2]; always @ (posedge clk) begin - if (we && (wa3 != 0)) regs[wa3] = wd3; + if (we && (wa3 != 0)) regs[wa3] <= wd3; end endmodule |