register file testbench

1 files changed, 8 insertions, 9 deletions

diff --git a/src/register_file.v b/src/register_file.v
index 81bce34..4846be8 100644
--- a/src/register_file.v
+++ b/src/register_file.v
@@ -5,25 +5,24 @@ module register_file #(
   input clk, rst, we,
   input [log2(N)-1:0] addr_rs0, addr_rs1, addr_rd2,
   input [N-1:0] data_rd2,
-  output [N-1:0] data_rs0, data_rs1
+  output reg [N-1:0] data_rs0, data_rs1
 );
 
 `include "include/log2.vh"
 
 reg [N-1:0] registers[XLEN-1:1];
 
-assign data_rs0 = (addr_rs0 == 0) ? 0 : registers[addr_rs0];
-assign data_rs1 = (addr_rs1 == 0) ? 0 : registers[addr_rs1];
-
-
-
 integer i;
-always @(posedge clk) begin
+always @(posedge clk or rst) begin
   if (rst) begin
     for (i = 1; i < XLEN; i = i + 1)
       registers[i] <= 0;
-  end else if (we && (addr_rd2 != 0)) begin
-    registers[addr_rd2] <= data_rd2;
+  end else begin
+    data_rs0 = (addr_rs0 == 0) ? 0 : registers[addr_rs0];
+    data_rs1 = (addr_rs1 == 0) ? 0 : registers[addr_rs1];
+    if (we && (addr_rd2 != 0)) begin
+      registers[addr_rd2] = data_rd2;
+    end
   end
 end