| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-05-21 | restructured project | Flavian Kaufmann | |
| 2024-05-13 | async reset | Flavian Kaufmann | |
| 2024-05-13 | refactoring, runs now on fpga | Flavian Kaufmann | |
| 2024-04-27 | added clock divider | Flavian Kaufmann | |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |