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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-04-27 14:52:08 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-04-27 14:52:08 +0200
commit08d6eea4fc23e7f569bbfd883f0dc049272a4b47 (patch)
tree9d4cc95e1911fed721848401209544b9fadbbf9b /src/clock_divider.v
parent7addab23add21dcb94bab5525787d1b97b11ce39 (diff)
downloadriscv_cpu-08d6eea4fc23e7f569bbfd883f0dc049272a4b47.tar.gz
riscv_cpu-08d6eea4fc23e7f569bbfd883f0dc049272a4b47.zip
added clock divider
Diffstat (limited to 'src/clock_divider.v')
-rw-r--r--src/clock_divider.v27
1 files changed, 27 insertions, 0 deletions
diff --git a/src/clock_divider.v b/src/clock_divider.v
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+++ b/src/clock_divider.v
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+module clock_divider #(
+ parameter N = 2
+)(
+ input clk,
+ input reset,
+ output reg clk_out
+);
+
+ reg [31:0] counter = 0;
+
+ always @(posedge clk or posedge reset) begin
+ if (reset) begin
+ counter <= 0;
+ clk_out <= 0;
+ end else begin
+ if (counter == (N-1)/2) begin
+ clk_out <= ~clk_out;
+ counter <= counter + 1;
+ end else if (counter >= (N-1)) begin
+ clk_out <= ~clk_out;
+ counter <= 0;
+ end else begin
+ counter <= counter + 1;
+ end
+ end
+ end
+endmodule