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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-21 13:50:28 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-21 13:50:28 +0200
commitcb0be9e2039569ee7d18657e8f675d1f8369b407 (patch)
tree91fa71b3960d1ad5217759371143efbdd833d475 /src/clock_divider.v
parent98d0dd96611dc2c0e444eaf9410f8adf2924c6b5 (diff)
downloadriscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.tar.gz
riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.zip
restructured project
Diffstat (limited to 'src/clock_divider.v')
-rw-r--r--src/clock_divider.v29
1 files changed, 0 insertions, 29 deletions
diff --git a/src/clock_divider.v b/src/clock_divider.v
deleted file mode 100644
index a63e943..0000000
--- a/src/clock_divider.v
+++ /dev/null
@@ -1,29 +0,0 @@
-module clock_divider #(
- parameter N = 2
-)(
- input clk,
- input rstn,
-
- output reg clk_div
-);
-
-reg [31:0] counter = 0;
-
-always @(posedge clk or negedge rstn) begin
- if (!rstn) begin
- counter <= 0;
- clk_div <= 0;
- end else begin
- if (counter == (N-1)/2) begin
- clk_div <= ~clk_div;
- counter <= counter + 1;
- end else if (counter >= (N-1)) begin
- clk_div <= ~clk_div;
- counter <= 0;
- end else begin
- counter <= counter + 1;
- end
- end
-end
-
-endmodule