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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 08:06:30 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 08:06:30 +0200 |
| commit | 05366e24d8b3cfca4b856b1b3740d535cbdf7dd7 (patch) | |
| tree | c24a7ab1b5f17db28391af6ff8d9c9ccc20bc94e /src/clock_divider.v | |
| parent | 48205bf3e8d421b6aa0474a4d120ae5faaaaa670 (diff) | |
| download | riscv_cpu-05366e24d8b3cfca4b856b1b3740d535cbdf7dd7.tar.gz riscv_cpu-05366e24d8b3cfca4b856b1b3740d535cbdf7dd7.zip | |
async reset
Diffstat (limited to 'src/clock_divider.v')
| -rw-r--r-- | src/clock_divider.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/clock_divider.v b/src/clock_divider.v index 0ece86d..a63e943 100644 --- a/src/clock_divider.v +++ b/src/clock_divider.v @@ -9,7 +9,7 @@ module clock_divider #( reg [31:0] counter = 0; -always @(posedge clk) begin +always @(posedge clk or negedge rstn) begin if (!rstn) begin counter <= 0; clk_div <= 0; |