| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-05-12 | refactoring | Flavian Kaufmann |
| 2024-05-09 | stopped initializing ram and register file to 0 at beginning | Flavian Kaufmann |
| 2024-05-07 | cpu | Flavian Kaufmann |
| 2024-05-05 | genrom | Flavian Kaufmann |
| 2024-05-05 | added memory unit | Flavian Kaufmann |
| 2024-05-05 | register file testbench | Flavian Kaufmann |
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index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
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