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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-07 17:27:41 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-07 17:27:41 +0200 |
| commit | 9d69eaa8e3be69ead0918d915bdacb7d0def9281 (patch) | |
| tree | ba08ada6f1a0ca95ace1311d176f265139ac95b9 /sim/testbench_register_file.v | |
| parent | f2e07b4ae7f4410efaf100e830a51d7dcb0d1b28 (diff) | |
| download | riscv_cpu-9d69eaa8e3be69ead0918d915bdacb7d0def9281.tar.gz riscv_cpu-9d69eaa8e3be69ead0918d915bdacb7d0def9281.zip | |
cpu
Diffstat (limited to 'sim/testbench_register_file.v')
| -rw-r--r-- | sim/testbench_register_file.v | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/sim/testbench_register_file.v b/sim/testbench_register_file.v index 79825dc..a22f3e1 100644 --- a/sim/testbench_register_file.v +++ b/sim/testbench_register_file.v @@ -14,12 +14,12 @@ register_file uut ( .clk(clk), .rst(rst), .we(we), - .addr_read0(addr_rs0), - .addr_read1(addr_rs1), - .addr_write2(addr_rd2), - .data_read0(data_rs0), - .data_read1(data_rs1), - .data_write2(data_rd2) + .rs1(addr_rs0), + .rs2(addr_rs1), + .rd(addr_rd2), + .rs1_data(data_rs0), + .rs2_data(data_rs1), + .rd_data(data_rd2) ); integer file, r, eof; |