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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-09 11:26:33 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-09 11:26:33 +0200
commit008059fbe4e960a10bb4c444013129e0aaa02818 (patch)
tree0e37db7e4ac82fc33c86e5f1dcaa0de59e983c73 /sim/testbench_register_file.v
parentd810d1cd42a31268ccb33993f1f1f429900c5ff8 (diff)
downloadriscv_cpu-008059fbe4e960a10bb4c444013129e0aaa02818.tar.gz
riscv_cpu-008059fbe4e960a10bb4c444013129e0aaa02818.zip
stopped initializing ram and register file to 0 at beginning
Diffstat (limited to 'sim/testbench_register_file.v')
-rw-r--r--sim/testbench_register_file.v9
1 files changed, 9 insertions, 0 deletions
diff --git a/sim/testbench_register_file.v b/sim/testbench_register_file.v
index a22f3e1..b0e0860 100644
--- a/sim/testbench_register_file.v
+++ b/sim/testbench_register_file.v
@@ -33,6 +33,7 @@ always #5 clk = ~clk;
reg [1023:0] testvec_filename;
reg [1023:0] waveform_filename;
+integer i;
initial begin
if ($value$plusargs("testvec=%s", testvec_filename)) begin
end else begin
@@ -69,6 +70,14 @@ initial begin
@(posedge clk);
rst = 0;
+ for (i = 0; i < 32; i = i + 1) begin
+ we = 1;
+ addr_rd2 = i;
+ data_rd2 = 32'b0;
+ @(posedge clk);
+ #1;
+ end
+
file = $fopen(testvec_filename, "r");
if (file == 0) begin
$display("ERROR: failed to open testvec");