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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-12 21:27:41 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-12 21:27:41 +0200 |
| commit | deb7d0a6fc76d5250c238d479cf97d4755abef01 (patch) | |
| tree | 395c266ff4757e83e151d1286d6d2388e63d9a9c /sim/testbench_register_file.v | |
| parent | 008059fbe4e960a10bb4c444013129e0aaa02818 (diff) | |
| download | riscv_cpu-deb7d0a6fc76d5250c238d479cf97d4755abef01.tar.gz riscv_cpu-deb7d0a6fc76d5250c238d479cf97d4755abef01.zip | |
refactoring
Diffstat (limited to 'sim/testbench_register_file.v')
| -rw-r--r-- | sim/testbench_register_file.v | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/sim/testbench_register_file.v b/sim/testbench_register_file.v index b0e0860..c1ca542 100644 --- a/sim/testbench_register_file.v +++ b/sim/testbench_register_file.v @@ -12,14 +12,14 @@ wire [31:0] data_rs0, data_rs1; register_file uut ( .clk(clk), - .rst(rst), + .rstn(!rst), .we(we), - .rs1(addr_rs0), - .rs2(addr_rs1), - .rd(addr_rd2), - .rs1_data(data_rs0), - .rs2_data(data_rs1), - .rd_data(data_rd2) + .ra1(addr_rs0), + .ra2(addr_rs1), + .wa3(addr_rd2), + .rd1(data_rs0), + .rd2(data_rs1), + .wd3(data_rd2) ); integer file, r, eof; |