refactoring, runs now on fpga

1 files changed, 1 insertions, 1 deletions

diff --git a/src/ram.v b/src/ram.v
index 1573de8..8234d5d 100644
--- a/src/ram.v
+++ b/src/ram.v
@@ -17,7 +17,7 @@ reg [8:0] memory [SIZE-1:0];
 assign data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
 
 
-always @(posedge clk /*or posedge rst*/) begin
+always @(posedge clk) begin
   if (we) begin
     { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write;
   end