refactoring

1 files changed, 3 insertions, 10 deletions

diff --git a/src/ram.v b/src/ram.v
index efcfc04..1573de8 100644
--- a/src/ram.v
+++ b/src/ram.v
@@ -17,17 +17,10 @@ reg [8:0] memory [SIZE-1:0];
 assign data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
 
 
-// integer i;
 always @(posedge clk /*or posedge rst*/) begin
-//  if (rst) begin
-//    for (i = 0; i < SIZE; i = i + 1)
-//      memory[i] <= 0;
-//  end else begin 
-    if (we) begin
-      { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write;
-    end
-//  end
-
+  if (we) begin
+    { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write;
+  end
 end
 
 endmodule