From 48205bf3e8d421b6aa0474a4d120ae5faaaaa670 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Mon, 13 May 2024 07:46:45 +0200 Subject: refactoring, runs now on fpga --- sim/testbench_cpu.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'sim') diff --git a/sim/testbench_cpu.v b/sim/testbench_cpu.v index d6c3975..87b34d2 100644 --- a/sim/testbench_cpu.v +++ b/sim/testbench_cpu.v @@ -7,7 +7,8 @@ reg rst; cpu cpu ( .clk(clk), - .rstn(!rst) + .rstn(!rst), + .dbg_t6(_) ); integer file, r, eof; @@ -55,7 +56,7 @@ initial begin while (1) begin @(posedge clk); clk_cycle_count = clk_cycle_count + 1; - if (clk_cycle_count == 100) $finish; + if (clk_cycle_count == 1000) $finish; end end -- cgit v1.2.3