| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | testbench_alu.v | 1808 | logplain |
| -rw-r--r-- | testbench_cpu.v | 961 | logplain |
| -rw-r--r-- | testbench_register_file.v | 2354 | logplain |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |
|
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |
| Mode | Name | Size | |
|---|---|---|---|
| -rw-r--r-- | testbench_alu.v | 1808 | logplain |
| -rw-r--r-- | testbench_cpu.v | 961 | logplain |
| -rw-r--r-- | testbench_register_file.v | 2354 | logplain |