align

1 files changed, 4 insertions, 4 deletions

diff --git a/rtl/src/data_reg.v b/rtl/src/data_reg.v
index 1b21a4e..65fe273 100644
--- a/rtl/src/data_reg.v
+++ b/rtl/src/data_reg.v
@@ -2,16 +2,16 @@
 // Stores output of memory unit for one more cycle.
 
 module data_reg (
-  input clk,
-  input rstn,
+  input             clk,
+  input             rstn,
 
-  input [31:0] data_in,
+  input      [31:0] data_in,
   output reg [31:0] data_buf
 );
 
 always @ (posedge clk or negedge rstn) begin
   if (!rstn) data_buf <= 32'b0;
-  else data_buf <= data_in;
+  else       data_buf <= data_in;
 end
 
 endmodule