From c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Thu, 23 May 2024 07:04:37 +0200 Subject: align --- rtl/src/data_reg.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'rtl/src/data_reg.v') diff --git a/rtl/src/data_reg.v b/rtl/src/data_reg.v index 1b21a4e..65fe273 100644 --- a/rtl/src/data_reg.v +++ b/rtl/src/data_reg.v @@ -2,16 +2,16 @@ // Stores output of memory unit for one more cycle. module data_reg ( - input clk, - input rstn, + input clk, + input rstn, - input [31:0] data_in, + input [31:0] data_in, output reg [31:0] data_buf ); always @ (posedge clk or negedge rstn) begin if (!rstn) data_buf <= 32'b0; - else data_buf <= data_in; + else data_buf <= data_in; end endmodule -- cgit v1.2.3