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-rw-r--r--prog/Makefile2
-rw-r--r--prog/src/main.c4
-rw-r--r--rtl/cst/tangnano9k.cst33
-rw-r--r--rtl/src/alu.v8
-rw-r--r--rtl/src/alu_a_src_mux.v10
-rw-r--r--rtl/src/alu_b_src_mux.v6
-rw-r--r--rtl/src/alu_op_decode.v12
-rw-r--r--rtl/src/alu_result_reg.v8
-rw-r--r--rtl/src/arithmetic_unit.v6
-rw-r--r--rtl/src/clock_divider.v10
-rw-r--r--rtl/src/control_unit.v44
-rw-r--r--rtl/src/cpu.v31
-rw-r--r--rtl/src/data_reg.v8
-rw-r--r--rtl/src/immediate_extend.v4
-rw-r--r--rtl/src/instruction_reg.v8
-rw-r--r--rtl/src/io.v12
-rw-r--r--rtl/src/logic_unit.v6
-rw-r--r--rtl/src/mem_addr_src_mux.v6
-rw-r--r--rtl/src/memory_interface.v58
-rw-r--r--rtl/src/pc_reg.v8
-rw-r--r--rtl/src/ram.v23
-rw-r--r--rtl/src/register_file.v14
-rw-r--r--rtl/src/register_file_reg.v8
-rw-r--r--rtl/src/reset_synchronizer.v4
-rw-r--r--rtl/src/result_mux.v8
-rw-r--r--rtl/src/rom.v20
-rw-r--r--rtl/src/shift_unit.v6
-rw-r--r--rtl/src/top.v11
28 files changed, 167 insertions, 211 deletions
diff --git a/prog/Makefile b/prog/Makefile
index a5dfeaa..11a1f9b 100644
--- a/prog/Makefile
+++ b/prog/Makefile
@@ -53,7 +53,7 @@ $(BUILD_DIR):
# create objdump of elf file and print
objdump: $(ELF_FILE)
- $(RISCV_OBJDUMP) -d -x --disassembler-color=on $(ELF_FILE)
+ $(RISCV_OBJDUMP) -D -x -s --disassembler-color=on $(ELF_FILE)
# display size information of elf file
size: $(ELF_FILE)
diff --git a/prog/src/main.c b/prog/src/main.c
index a31196f..a721e14 100644
--- a/prog/src/main.c
+++ b/prog/src/main.c
@@ -6,7 +6,7 @@ volatile uint32_t *io_out = (volatile uint32_t *)0x00000004;
int main(void) {
while (1) {
- if (*io_in) *io_out = 0b00000;
- else *io_out = 0b11111;
+ if (*io_in) *io_out = 0b11111;
+ else *io_out = 0b00000;
}
}
diff --git a/rtl/cst/tangnano9k.cst b/rtl/cst/tangnano9k.cst
index e909e36..1e939f5 100644
--- a/rtl/cst/tangnano9k.cst
+++ b/rtl/cst/tangnano9k.cst
@@ -1,38 +1,11 @@
//Part Number: GW1NR-LV9QN88PC6/I5
-IO_LOC "clk" 52;
+IO_LOC "clk" 52;
IO_LOC "led[0]" 10;
IO_LOC "led[1]" 11;
IO_LOC "led[2]" 13;
IO_LOC "led[3]" 14;
IO_LOC "led[4]" 15;
IO_LOC "led[5]" 16;
-IO_LOC "key" 3;
-IO_LOC "rst" 4;
-
-IO_LOC "LCD_B[0]" 54;
-IO_LOC "LCD_B[1]" 53;
-IO_LOC "LCD_B[2]" 51;
-IO_LOC "LCD_B[3]" 42;
-IO_LOC "LCD_B[4]" 41;
-IO_LOC "LCD_CLK" 35;
-IO_LOC "LCD_DEN" 33;
-IO_LOC "LCD_G[0]" 70;
-IO_LOC "LCD_G[1]" 69;
-IO_LOC "LCD_G[2]" 68;
-IO_LOC "LCD_G[3]" 57;
-IO_LOC "LCD_G[4]" 56;
-IO_LOC "LCD_G[5]" 55;
-IO_LOC "LCD_HYNC" 40;
-IO_LOC "LCD_R[0]" 75;
-IO_LOC "LCD_R[1]" 74;
-IO_LOC "LCD_R[2]" 73;
-IO_LOC "LCD_R[3]" 72;
-IO_LOC "LCD_R[4]" 71;
-IO_LOC "LCD_SYNC" 34;
-IO_LOC "LCD_XR" 32;
-IO_LOC "LCD_XL" 39;
-
-
-// true LVDS pins
-IO_LOC "tlvds_p" 25,26;
+IO_LOC "s2" 3;
+IO_LOC "s1" 4;
diff --git a/rtl/src/alu.v b/rtl/src/alu.v
index 2e927ca..21b9dc0 100644
--- a/rtl/src/alu.v
+++ b/rtl/src/alu.v
@@ -3,13 +3,13 @@
// The signal zero is high if result is zero.
module alu (
- input [31:0] a,
- input [31:0] b,
+ input [31:0] a,
+ input [31:0] b,
- input [3:0] op,
+ input [3:0] op,
output reg [31:0] result,
- output zero
+ output zero
);
wire [31:0] arithmetic_result, logic_result, shift_result;
diff --git a/rtl/src/alu_a_src_mux.v b/rtl/src/alu_a_src_mux.v
index 4c68d8d..702f92a 100644
--- a/rtl/src/alu_a_src_mux.v
+++ b/rtl/src/alu_a_src_mux.v
@@ -2,12 +2,12 @@
// Selects source for alu input a.
module alu_a_src_mux (
- input [31:0] src_pc,
- input [31:0] src_pc_buf,
- input [31:0] src_rd1,
- input [31:0] src_rd1_buf,
+ input [31:0] src_pc,
+ input [31:0] src_pc_buf,
+ input [31:0] src_rd1,
+ input [31:0] src_rd1_buf,
- input [2:0] alu_a_src,
+ input [2:0] alu_a_src,
output reg [31:0] alu_a
);
diff --git a/rtl/src/alu_b_src_mux.v b/rtl/src/alu_b_src_mux.v
index 5f188bc..7730225 100644
--- a/rtl/src/alu_b_src_mux.v
+++ b/rtl/src/alu_b_src_mux.v
@@ -2,10 +2,10 @@
// Selects source for alu input b.
module alu_b_src_mux (
- input [31:0] src_rd2_buf,
- input [31:0] src_imm,
+ input [31:0] src_rd2_buf,
+ input [31:0] src_imm,
- input [1:0] alu_b_src,
+ input [1:0] alu_b_src,
output reg [31:0] alu_b
);
diff --git a/rtl/src/alu_op_decode.v b/rtl/src/alu_op_decode.v
index 0e985eb..0866bbe 100644
--- a/rtl/src/alu_op_decode.v
+++ b/rtl/src/alu_op_decode.v
@@ -5,11 +5,11 @@
// the next address of the pc.
module alu_op_decode (
- input [6:0] opcode,
- input [2:0] funct3,
- input [6:0] funct7,
+ input [6:0] opcode,
+ input [2:0] funct3,
+ input [6:0] funct7,
- input alu_ctrl,
+ input alu_ctrl,
output reg [3:0] alu_op
);
@@ -18,7 +18,7 @@ module alu_op_decode (
always @ (*) begin
if (alu_ctrl == ALU_CTRL_ADD) begin
- alu_op = ALU_OP_ADD;
+ alu_op = ALU_OP_ADD;
end else if (opcode == OPCODE_REG || opcode == OPCODE_IMM) begin // instruction is of r-type or i-type
case (funct3)
FUNCT3_ALU_ADD_SUB: alu_op = (opcode == OPCODE_REG && funct7 == FUNCT7_ALU_SUB) ? ALU_OP_SUB : ALU_OP_ADD;
@@ -45,7 +45,7 @@ always @ (*) begin
default: alu_op = ALU_OP_ADD;
endcase
end else begin
- alu_op = ALU_OP_ADD;
+ alu_op = ALU_OP_ADD;
end
end
diff --git a/rtl/src/alu_result_reg.v b/rtl/src/alu_result_reg.v
index 377760a..dc78c38 100644
--- a/rtl/src/alu_result_reg.v
+++ b/rtl/src/alu_result_reg.v
@@ -3,16 +3,16 @@
// This is used for example on load/store, alu wb, etc.
module alu_result_reg (
- input clk,
- input rstn,
+ input clk,
+ input rstn,
- input [31:0] alu_result_in,
+ input [31:0] alu_result_in,
output reg [31:0] alu_result_buf
);
always @ (posedge clk or negedge rstn) begin
if (!rstn) alu_result_buf <= 32'b0;
- else alu_result_buf <= alu_result_in;
+ else alu_result_buf <= alu_result_in;
end
endmodule
diff --git a/rtl/src/arithmetic_unit.v b/rtl/src/arithmetic_unit.v
index e987dbd..67ca4bc 100644
--- a/rtl/src/arithmetic_unit.v
+++ b/rtl/src/arithmetic_unit.v
@@ -2,10 +2,10 @@
// Arithmetic part of the alu.
module arithmetic_unit (
- input [31:0] a,
- input [31:0] b,
+ input [31:0] a,
+ input [31:0] b,
- input [1:0] op,
+ input [1:0] op,
output reg [31:0] result
);
diff --git a/rtl/src/clock_divider.v b/rtl/src/clock_divider.v
index e673a43..8d25fdf 100644
--- a/rtl/src/clock_divider.v
+++ b/rtl/src/clock_divider.v
@@ -3,10 +3,10 @@
// to decrease its frequency, useful for debugging for example.
module clock_divider #(
- parameter N = 2
+ parameter N = 2
)(
- input clk,
- input rstn,
+ input clk,
+ input rstn,
output reg clk_div
);
@@ -15,8 +15,8 @@ reg [31:0] counter = 0;
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
- counter <= 0;
- clk_div <= 0;
+ counter <= 0;
+ clk_div <= 0;
end else begin
if (counter == (N-1)/2) begin
clk_div <= ~clk_div;
diff --git a/rtl/src/control_unit.v b/rtl/src/control_unit.v
index f259506..6849214 100644
--- a/rtl/src/control_unit.v
+++ b/rtl/src/control_unit.v
@@ -3,26 +3,26 @@
// manages its state.
module control_unit (
- input clk,
- input rstn,
+ input clk,
+ input rstn,
- input [31:0] instr,
- input alu_zero,
+ input [31:0] instr,
+ input alu_zero,
output reg [2:0] imm_src,
- output pc_we,
+ output pc_we,
- output reg mem_addr_src,
- output reg mem_we,
+ output reg mem_addr_src,
+ output reg mem_we,
- output reg instr_we,
+ output reg instr_we,
- output reg rf_we,
- output [4:0] ra1, ra2, wa3,
+ output reg rf_we,
+ output [4:0] ra1, ra2, wa3,
output reg [2:0] alu_a_src,
output reg [1:0] alu_b_src,
- output [3:0] alu_op,
+ output [3:0] alu_op,
output reg [1:0] result_src
);
@@ -80,7 +80,7 @@ reg [3:0] state, next_state;
always @ (posedge clk or negedge rstn) begin
if (!rstn) state <= STATE_FETCH;
- else state <= next_state;
+ else state <= next_state;
end
// next state logic
@@ -122,16 +122,16 @@ end
// output/control logic
always @ (*) begin
- mem_addr_src = MEM_ADDR_SRC_RESULT;
- alu_a_src = ALU_A_SRC_RD1_BUF;
- alu_b_src = ALU_B_SRC_RD2_BUF;
- alu_ctrl = ALU_CTRL_OP;
- result_src = RESULT_SRC_ALU_RESULT;
- mem_we = MEM_WE_DISABLE;
- rf_we = RF_WE_DISABLE;
- instr_we = INSTR_WE_DISABLE;
- pc_update = PC_UPDATE_DISABLE;
- branch = BRANCH_DISABLE;
+ mem_addr_src = MEM_ADDR_SRC_RESULT;
+ alu_a_src = ALU_A_SRC_RD1_BUF;
+ alu_b_src = ALU_B_SRC_RD2_BUF;
+ alu_ctrl = ALU_CTRL_OP;
+ result_src = RESULT_SRC_ALU_RESULT;
+ mem_we = MEM_WE_DISABLE;
+ rf_we = RF_WE_DISABLE;
+ instr_we = INSTR_WE_DISABLE;
+ pc_update = PC_UPDATE_DISABLE;
+ branch = BRANCH_DISABLE;
case(state)
STATE_FETCH: begin
mem_addr_src = MEM_ADDR_SRC_PC;
diff --git a/rtl/src/cpu.v b/rtl/src/cpu.v
index 64e3d49..5e454fb 100644
--- a/rtl/src/cpu.v
+++ b/rtl/src/cpu.v
@@ -2,43 +2,42 @@
// Connects the various bit and pieces together.
module cpu (
- input clk,
- input rstn,
- input [31:0] io_in,
+ input clk,
+ input rstn,
+ input [31:0] io_in,
output [31:0] io_out
);
-
wire [31:0] pc, pc_buf;
-wire pc_we;
+wire pc_we;
wire [31:0] mem_addr;
-wire mem_addr_src;
+wire mem_addr_src;
wire [31:0] mem_rd;
-wire mem_we;
+wire mem_we;
-wire instr_we;
+wire instr_we;
wire [31:0] instr;
wire [31:0] imm;
-wire [2:0] imm_src;
+wire [2:0] imm_src;
wire [31:0] data_buf;
-wire rf_we;
-wire [4:0] ra1, ra2, wa3;
+wire rf_we;
+wire [4:0] ra1, ra2, wa3;
wire [31:0] rd1, rd2;
wire [31:0] rd1_buf, rd2_buf;
wire [31:0] alu_a, alu_b;
-wire [2:0] alu_a_src;
-wire [1:0] alu_b_src;
-wire [3:0] alu_op;
+wire [2:0] alu_a_src;
+wire [1:0] alu_b_src;
+wire [3:0] alu_op;
wire [31:0] alu_result;
-wire alu_zero;
+wire alu_zero;
wire [31:0] alu_result_buf;
-wire [1:0] result_src;
+wire [1:0] result_src;
wire [31:0] result;
diff --git a/rtl/src/data_reg.v b/rtl/src/data_reg.v
index 1b21a4e..65fe273 100644
--- a/rtl/src/data_reg.v
+++ b/rtl/src/data_reg.v
@@ -2,16 +2,16 @@
// Stores output of memory unit for one more cycle.
module data_reg (
- input clk,
- input rstn,
+ input clk,
+ input rstn,
- input [31:0] data_in,
+ input [31:0] data_in,
output reg [31:0] data_buf
);
always @ (posedge clk or negedge rstn) begin
if (!rstn) data_buf <= 32'b0;
- else data_buf <= data_in;
+ else data_buf <= data_in;
end
endmodule
diff --git a/rtl/src/immediate_extend.v b/rtl/src/immediate_extend.v
index 2b38081..156ce20 100644
--- a/rtl/src/immediate_extend.v
+++ b/rtl/src/immediate_extend.v
@@ -2,8 +2,8 @@
// Extracts immediate value from various instruction formats.
module immediate_extend (
- input [31:0] instr,
- input [2:0] imm_src,
+ input [31:0] instr,
+ input [2:0] imm_src,
output reg [31:0] imm
);
diff --git a/rtl/src/instruction_reg.v b/rtl/src/instruction_reg.v
index d2146b4..305789e 100644
--- a/rtl/src/instruction_reg.v
+++ b/rtl/src/instruction_reg.v
@@ -2,11 +2,11 @@
// Stores current instruction (and pc) until next one gets fetched.
module instruction_reg (
- input clk,
- input rstn,
+ input clk,
+ input rstn,
- input we,
- input [31:0] pc_in, instr_in,
+ input we,
+ input [31:0] pc_in, instr_in,
output reg [31:0] pc_buf, instr
);
diff --git a/rtl/src/io.v b/rtl/src/io.v
index 7d6cd4f..f872b83 100644
--- a/rtl/src/io.v
+++ b/rtl/src/io.v
@@ -2,16 +2,16 @@
// Input and output register, connected to pins of fpga.
module io (
- input clk,
- input rstn,
+ input clk,
+ input rstn,
- input we,
- input [31:0] addr,
- input [31:0] wd,
+ input we,
+ input [31:0] addr,
+ input [31:0] wd,
output reg [31:0] rd,
- input [31:0] io_in,
+ input [31:0] io_in,
output reg [31:0] io_out
);
diff --git a/rtl/src/logic_unit.v b/rtl/src/logic_unit.v
index fad0287..8857202 100644
--- a/rtl/src/logic_unit.v
+++ b/rtl/src/logic_unit.v
@@ -2,10 +2,10 @@
// Logic part of alu.
module logic_unit (
- input [31:0] a,
- input [31:0] b,
+ input [31:0] a,
+ input [31:0] b,
- input [1:0] op,
+ input [1:0] op,
output reg [31:0] result
);
diff --git a/rtl/src/mem_addr_src_mux.v b/rtl/src/mem_addr_src_mux.v
index 4ab4509..ae6b3d1 100644
--- a/rtl/src/mem_addr_src_mux.v
+++ b/rtl/src/mem_addr_src_mux.v
@@ -2,10 +2,10 @@
// Selects source mem addr.
module mem_addr_src_mux (
- input [31:0] src_pc,
- input [31:0] src_result,
+ input [31:0] src_pc,
+ input [31:0] src_result,
- input mem_addr_src,
+ input mem_addr_src,
output reg [31:0] mem_addr
);
diff --git a/rtl/src/memory_interface.v b/rtl/src/memory_interface.v
index 01dfa39..055016e 100644
--- a/rtl/src/memory_interface.v
+++ b/rtl/src/memory_interface.v
@@ -2,42 +2,42 @@
// Connects rom, ram and io to memory bus.
module memory_interface (
- input clk,
- input rstn,
+ input clk,
+ input rstn,
- input we,
- input [31:0] addr,
- input [31:0] wd,
+ input we,
+ input [31:0] addr,
+ input [31:0] wd,
output reg [31:0] rd,
- input [31:0] io_in,
- output [31:0] io_out
+ input [31:0] io_in,
+ output [31:0] io_out
);
`include "include/consts.vh"
-reg ram_we;
-reg io_we;
+reg ram_we;
+reg io_we;
wire [31:0] ram_rd, rom_rd;
-reg [31:0] rel_addr;
+reg [31:0] rel_addr;
-ram #(.N(32), .SIZE(1024)) ram(
+ram #(.SIZE(1024)) ram (
.clk(clk),
.rstn(rstn),
.we(ram_we),
.addr(rel_addr),
- .data_read(ram_rd),
- .data_write(wd)
+ .rd(ram_rd),
+ .wd(wd)
);
-rom #(.N(32), .SIZE(1024), .ROM_FILE("../../build/rom.hex")) rom(
+rom #(.SIZE(1024)) rom (
.clk(clk),
.addr(rel_addr),
- .data_read(rom_rd)
+ .rd(rom_rd)
);
-io io(
+io io (
.clk(clk),
.rstn(rstn),
.we(io_we),
@@ -48,33 +48,19 @@ io io(
.io_out(io_out)
);
-
-// 0000 0000 Reserved
-// 0000 FFFF
-//
-// 0001 0000 ROM
-// 000F FFFF
-//
-// 0010 0000 RAM
-// FF0F FFFF
-//
-// FF10 0000 Reserved
-// FFFF FFFF
-
-
always @ (*) begin
- rd = 0;
- rel_addr = 0;
- ram_we = 0;
- io_we = 0;
- if ( addr >= ROM_BEGIN && addr <= ROM_END) begin
+ rd = 0;
+ rel_addr = 0;
+ ram_we = 0;
+ io_we = 0;
+ if (addr >= ROM_BEGIN && addr <= ROM_END) begin
rd = rom_rd;
rel_addr = addr - ROM_BEGIN;
end else if (addr >= RAM_BEGIN && addr <= RAM_END) begin
ram_we = we;
rd = ram_rd;
rel_addr = addr - RAM_BEGIN;
- end else if (addr >= IO_BEGIN && addr <= IO_END) begin
+ end else if (addr >= IO_BEGIN && addr <= IO_END) begin
io_we = we;
rd = io_rd;
rel_addr = addr - IO_BEGIN;
diff --git a/rtl/src/pc_reg.v b/rtl/src/pc_reg.v
index af6f1ea..ac2ff50 100644
--- a/rtl/src/pc_reg.v
+++ b/rtl/src/pc_reg.v
@@ -2,11 +2,11 @@
// Stores current pc.
module pc_reg (
- input clk,
- input rstn,
+ input clk,
+ input rstn,
- input we,
- input [31:0] pc_in,
+ input we,
+ input [31:0] pc_in,
output reg [31:0] pc
);
diff --git a/rtl/src/ram.v b/rtl/src/ram.v
index 7595e89..c0ec231 100644
--- a/rtl/src/ram.v
+++ b/rtl/src/ram.v
@@ -1,26 +1,25 @@
// ram:
// Contains data section of program and is used for stack/heap, etc.
-module ram #(
- parameter N = 32,
- parameter SIZE = 1024
+module ram #(
+ parameter SIZE = 1024
)(
- input clk,
- input rstn,
- input we,
- input [N-1:0] addr,
- input [N-1:0] data_write,
- output reg [N-1:0] data_read
+ input clk,
+ input rstn,
+ input we,
+ input [31:0] addr,
+ input [31:0] wd,
+ output reg [31:0] rd
);
`include "include/log2.vh"
//(* RAM_STYLE="BLOCK" *)
-reg [N-1:0] mem [0:SIZE-1];
+reg [31:0] mem [0:SIZE-1];
always @(posedge clk) begin
- if (we) mem[addr >> 2] <= data_write;
- data_read <= mem[addr >> 2];
+ if (we) mem[addr >> 2] <= wd;
+ rd <= mem[addr >> 2];
end
endmodule
diff --git a/rtl/src/register_file.v b/rtl/src/register_file.v
index ad3f5fe..550484d 100644
--- a/rtl/src/register_file.v
+++ b/rtl/src/register_file.v
@@ -2,15 +2,15 @@
// Registers of the cpu.
module register_file (
- input clk,
- input rstn,
+ input clk,
+ input rstn,
- input we,
- input [4:0] ra1,
- input [4:0] ra2,
- input [4:0] wa3,
+ input we,
+ input [4:0] ra1,
+ input [4:0] ra2,
+ input [4:0] wa3,
- input [31:0] wd3,
+ input [31:0] wd3,
output [31:0] rd1,
output [31:0] rd2
diff --git a/rtl/src/register_file_reg.v b/rtl/src/register_file_reg.v
index 049f53c..7d9cc03 100644
--- a/rtl/src/register_file_reg.v
+++ b/rtl/src/register_file_reg.v
@@ -2,11 +2,11 @@
// Stores outputs of register file for one more clock cycle.
module register_file_reg (
- input clk,
- input rstn,
+ input clk,
+ input rstn,
- input [31:0] rd1_in,
- input [31:0] rd2_in,
+ input [31:0] rd1_in,
+ input [31:0] rd2_in,
output reg [31:0] rd1_buf,
output reg [31:0] rd2_buf
diff --git a/rtl/src/reset_synchronizer.v b/rtl/src/reset_synchronizer.v
index 3d68bf7..dc03579 100644
--- a/rtl/src/reset_synchronizer.v
+++ b/rtl/src/reset_synchronizer.v
@@ -4,8 +4,8 @@
// asynchronously with respect to the clock, it can cause metastability issues.
module reset_synchronizer (
- input clk,
- input rstn_async,
+ input clk,
+ input rstn_async,
output rstn
);
diff --git a/rtl/src/result_mux.v b/rtl/src/result_mux.v
index 5cbacb0..c2e6636 100644
--- a/rtl/src/result_mux.v
+++ b/rtl/src/result_mux.v
@@ -2,11 +2,11 @@
// Selects source for result.
module result_mux (
- input [31:0] src_alu_result,
- input [31:0] src_alu_result_buf,
- input [31:0] src_data_buf,
+ input [31:0] src_alu_result,
+ input [31:0] src_alu_result_buf,
+ input [31:0] src_data_buf,
- input [1:0] result_src,
+ input [1:0] result_src,
output reg [31:0] result
);
diff --git a/rtl/src/rom.v b/rtl/src/rom.v
index f32b9a0..60ca6e1 100644
--- a/rtl/src/rom.v
+++ b/rtl/src/rom.v
@@ -2,27 +2,27 @@
// Contains instructions of program.
module rom #(
- parameter N = 32,
- parameter SIZE = 1024,
- parameter ROM_FILE = "../../build/rom.hex"
+ parameter SIZE = 1024,
+ parameter ROM_FILE = "../../build/rom.hex"
)(
- input clk,
- input [N-1:0] addr,
- output reg [N-1:0] data_read
+ input clk,
+ input [31:0] addr,
+ output reg [31:0] rd
);
-`include "include/log2.vh"
+`include "include/consts.vh"
+
//(* RAM_STYLE="BLOCK" *)
-reg [N-1:0] mem [0:SIZE-1];
+reg [31:0] mem [0:SIZE-1];
initial begin
$readmemh(ROM_FILE, mem, 0, SIZE-1);
end
-always @(negedge clk) begin
- data_read <= mem[addr >> 2];
+always @ (negedge clk) begin
+ rd <= mem[addr >> 2];
end
endmodule
diff --git a/rtl/src/shift_unit.v b/rtl/src/shift_unit.v
index 7dbe4a2..5a1dfc4 100644
--- a/rtl/src/shift_unit.v
+++ b/rtl/src/shift_unit.v
@@ -3,11 +3,11 @@
module shift_unit (
input signed [31:0] a,
- input [4:0] b,
+ input [4:0] b,
- input [1:0] op,
+ input [1:0] op,
- output reg [31:0] result
+ output reg [31:0] result
);
`include "include/consts.vh"
diff --git a/rtl/src/top.v b/rtl/src/top.v
index d21f807..02ab48c 100644
--- a/rtl/src/top.v
+++ b/rtl/src/top.v
@@ -2,14 +2,13 @@
// Top module, maps signals to fpga.
module top (
- input clk,
- input key,
- input rst,
+ input clk,
+ input s1, s2,
output [5:0] led
);
-wire rstn, rstn_async, clk_cpu;
-assign rstn_async = rst;
+wire rstn, rstn_async, clk_cpu;
+assign rstn_async = s1;
wire [31:0] io_in;
wire [31:0] io_out;
@@ -28,7 +27,7 @@ clock_divider #(.N(1)) clkdiv (
assign led[0] = ~clk_cpu;
assign led[5:1] = ~io_out[4:0];
-assign io_in[0] = key;
+assign io_in[0] = ~s2;
cpu cpu (
generated by cgit v1.2.3 (git 2.46.0) at 2025-08-31 16:01:34 +0000