align

1 files changed, 4 insertions, 4 deletions

diff --git a/rtl/src/alu.v b/rtl/src/alu.v
index 2e927ca..21b9dc0 100644
--- a/rtl/src/alu.v
+++ b/rtl/src/alu.v
@@ -3,13 +3,13 @@
 // The signal zero is high if result is zero.
 
 module alu (
-  input [31:0] a, 
-  input [31:0] b,
+  input      [31:0] a, 
+  input      [31:0] b,
 
-  input [3:0] op,
+  input       [3:0] op,
   
   output reg [31:0] result,
-  output zero
+  output            zero
 );
 
 wire [31:0] arithmetic_result, logic_result, shift_result;