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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 15:57:42 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-21 15:57:42 +0200 |
| commit | ee94c97e4f8208d0c7404887cda16d00f67c6f1f (patch) | |
| tree | c31a0cc782e66d6bf68d82f684c1e5e167dab968 /rtl/src/alu.v | |
| parent | 99a50ce584cd29bcef7ed31cb9d933d0ae2e61ee (diff) | |
| download | riscv_cpu-ee94c97e4f8208d0c7404887cda16d00f67c6f1f.tar.gz riscv_cpu-ee94c97e4f8208d0c7404887cda16d00f67c6f1f.zip | |
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Diffstat (limited to 'rtl/src/alu.v')
| -rw-r--r-- | rtl/src/alu.v | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/rtl/src/alu.v b/rtl/src/alu.v index 8a265ee..2e927ca 100644 --- a/rtl/src/alu.v +++ b/rtl/src/alu.v @@ -1,3 +1,7 @@ +// alu: +// Computes result based on operands a, b and the provided operation. +// The signal zero is high if result is zero. + module alu ( input [31:0] a, input [31:0] b, |