From c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Thu, 23 May 2024 07:04:37 +0200 Subject: align --- rtl/src/alu.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'rtl/src/alu.v') diff --git a/rtl/src/alu.v b/rtl/src/alu.v index 2e927ca..21b9dc0 100644 --- a/rtl/src/alu.v +++ b/rtl/src/alu.v @@ -3,13 +3,13 @@ // The signal zero is high if result is zero. module alu ( - input [31:0] a, - input [31:0] b, + input [31:0] a, + input [31:0] b, - input [3:0] op, + input [3:0] op, output reg [31:0] result, - output zero + output zero ); wire [31:0] arithmetic_result, logic_result, shift_result; -- cgit v1.2.3