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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-06-28 16:10:11 +0200 |
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| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-06-28 16:10:11 +0200 |
| commit | 04a934987445897a03652aa73e2a5c5088d40ba1 (patch) | |
| tree | eb9ecb1cf1a68ef5fa602d0581b8046b39fe8406 /README.md | |
| parent | 94954f13818a55aae02b660942abd12dab32372d (diff) | |
| download | riscv_cpu-04a934987445897a03652aa73e2a5c5088d40ba1.tar.gz riscv_cpu-04a934987445897a03652aa73e2a5c5088d40ba1.zip | |
Diffstat (limited to 'README.md')
| -rw-r--r-- | README.md | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -2,7 +2,7 @@ An attempt at building a simple RISCV CPU in verilog. Currently my CPU implements the RV32I ISA without FENCE/ECALL/EBREAK instructions. The design -is very much based on David and Sarah Harris' book +is very much based on David and Sarah Harris' book "Digital Design and Computer Architecture (RISC-V Edition)". ## FPGA @@ -94,6 +94,7 @@ riscv_cpu * [Operating Systems: Three Easy Pieces by Remzi and Andrea Arpaci-Dusseau](https://pages.cs.wisc.edu/~remzi/OSTEP/) * [Example RISCV Cores](https://github.com/yunchenlo/awesome-RISCV-Cores) * [godbolt (compiler explorer)](https://godbolt.org) +* [DDCA Notes](https://github.com/flavian112/ethz_ddca) ## Design |