added ddca notes referenceHEADmaster

3 files changed, 11 insertions, 10 deletions

diff --git a/README.md b/README.md
index 122a11d..3befdd9 100644
--- a/README.md
+++ b/README.md
@@ -2,7 +2,7 @@
 
 An attempt at building a simple RISCV CPU in verilog. Currently my CPU
 implements the RV32I ISA without FENCE/ECALL/EBREAK instructions. The design
-is very much based on David and Sarah Harris' book 
+is very much based on David and Sarah Harris' book
 "Digital Design and Computer Architecture (RISC-V Edition)".
 
 ## FPGA
@@ -94,6 +94,7 @@ riscv_cpu
 * [Operating Systems: Three Easy Pieces by Remzi and Andrea Arpaci-Dusseau](https://pages.cs.wisc.edu/~remzi/OSTEP/)
 * [Example RISCV Cores](https://github.com/yunchenlo/awesome-RISCV-Cores)
 * [godbolt (compiler explorer)](https://godbolt.org)
+* [DDCA Notes](https://github.com/flavian112/ethz_ddca)
 
 ## Design
 
diff --git a/prog/src/startup.c b/prog/src/startup.c
index b587a95..ad9b9b6 100644
--- a/prog/src/startup.c
+++ b/prog/src/startup.c
@@ -5,15 +5,16 @@ extern unsigned int _sbss;   // start of .bss section
 extern unsigned int _ebss;   // end   of .bss section
 extern unsigned int _estack; // end   of .stack section (stack top)
 
-//void main(void); // main function declaration
+extern void main(void); // main function declaration
 
 extern void test_prog(void);
 
-void _start(void) __attribute__((section(".text.startup"), naked)); // entry point, cpu starts executing from here
-
 void _start(void)
-{
-  //test_prog();
+    __attribute__((section(".text.startup"),
+                   naked)); // entry point, cpu starts executing from here
+
+void _start(void) {
+  // test_prog();
 
   unsigned int *src, *dst;
 
@@ -29,11 +30,12 @@ void _start(void)
   }
 
   // initialize stack pointer
-  asm volatile ("la sp, _estack");
+  asm volatile("la sp, _estack");
 
   // call main function
   main();
 
   // halt
-  while (1);
+  while (1)
+    ;
 }
diff --git a/rtl/src/rom.v b/rtl/src/rom.v
index 9ade9bc..784e50d 100644
--- a/rtl/src/rom.v
+++ b/rtl/src/rom.v
@@ -18,8 +18,6 @@ module rom #(
 //(* RAM_STYLE="BLOCK" *)
 reg [31:0] mem [0:SIZE-1];
 
-reg [7:0] mem0, mem1, mem2, mem3;
-
 reg [31:0] rd_reg;
 reg [31:0] addr_reg;