From 04a934987445897a03652aa73e2a5c5088d40ba1 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Fri, 28 Jun 2024 16:10:11 +0200 Subject: added ddca notes reference --- README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'README.md') diff --git a/README.md b/README.md index 122a11d..3befdd9 100644 --- a/README.md +++ b/README.md @@ -2,7 +2,7 @@ An attempt at building a simple RISCV CPU in verilog. Currently my CPU implements the RV32I ISA without FENCE/ECALL/EBREAK instructions. The design -is very much based on David and Sarah Harris' book +is very much based on David and Sarah Harris' book "Digital Design and Computer Architecture (RISC-V Edition)". ## FPGA @@ -94,6 +94,7 @@ riscv_cpu * [Operating Systems: Three Easy Pieces by Remzi and Andrea Arpaci-Dusseau](https://pages.cs.wisc.edu/~remzi/OSTEP/) * [Example RISCV Cores](https://github.com/yunchenlo/awesome-RISCV-Cores) * [godbolt (compiler explorer)](https://godbolt.org) +* [DDCA Notes](https://github.com/flavian112/ethz_ddca) ## Design -- cgit v1.2.3