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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-23 20:59:16 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-23 20:59:16 +0200 |
| commit | 94954f13818a55aae02b660942abd12dab32372d (patch) | |
| tree | 1441a298ab7bed9f5144ebb5fceb8d388b012830 /README.md | |
| parent | 1a536e6ed689b8d7d3659a5dc19c28428e737b30 (diff) | |
| download | riscv_cpu-94954f13818a55aae02b660942abd12dab32372d.tar.gz riscv_cpu-94954f13818a55aae02b660942abd12dab32372d.zip | |
added course resource
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| -rw-r--r-- | README.md | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -89,6 +89,7 @@ riscv_cpu * [RISC-V ISA](https://riscv.org/specifications/) * [Digital Design and Computer Architecture by David and Sarah Harris](https://pages.hmc.edu/harris/ddca/) +* [DDCA Course by SAFARI Research Group, ETH Zürich](https://safari.ethz.ch/digitaltechnik) * [Computer Organization and Design by David Patterson](https://shop.elsevier.com/books/computer-organization-and-design-risc-v-edition/patterson/978-0-12-820331-6) * [Operating Systems: Three Easy Pieces by Remzi and Andrea Arpaci-Dusseau](https://pages.cs.wisc.edu/~remzi/OSTEP/) * [Example RISCV Cores](https://github.com/yunchenlo/awesome-RISCV-Cores) |