blob: 92b14a2d0d70ad8945d63782304309db5e1c0385 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
|
module ram #(
parameter N = 32,
parameter SIZE = 1024
)(
input clk,
input rst,
input we,
input [log2(SIZE)-1:0] addr,
input [N-1:0] data_write,
output reg [N-1:0] data_read
);
`include "include/log2.vh"
reg [8:0] memory [SIZE-1:0];
integer i;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (i = 0; i < SIZE; i = i + 1)
memory[i] <= 0;
end else begin
if (we) begin
{ memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write;
end
data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
end
end
endmodule
|
