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Diffstat (limited to 'src/cpu.v')
-rw-r--r-- | src/cpu.v | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -7,6 +7,7 @@ module cpu ( // Control Unit wire mem_addr_src; +wire mem_we; wire pc_we; wire instr_we; wire rf_we; |
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index : riscv_cpu.git | |
Simple RISC-V CPU written in Verilog |
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