src/top.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

module top (
	input clk,
	input key,
	output [5:0] led
);

reg [25:0] ctr_q;
wire [25:0] ctr_d;

// Sequential code (flip-flop)
always @(posedge clk) begin
	if (key) begin
		ctr_q <= ctr_d;
	end
end

// Combinational code (boolean logic)
assign ctr_d = ctr_q + 1'b1;
assign led = ctr_q[25:20];

endmodule