blob: 86f26ce652243488b1c7ef79fdd6a5099c37f739 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
|
module top (
input clk,
input key,
output [5:0] led
);
wire rstn, clk_cpu;
assign rstn = key;
wire [31:0] io_in;
wire [31:0] io_out;
clock_divider #(.N(1024 * 1024)) clkdiv (
.clk(clk),
.rstn(rstn),
.clk_div(clk_cpu)
);
assign led[0] = ~clk_cpu;
assign led[5:1] = ~io_out[4:0];
cpu cpu (
.clk(clk_cpu),
.rstn(rstn),
.io_in(io_in),
.io_out(io_out)
);
endmodule
|
