From 14e5e2120e1176ce63f73adddd102934144c0f12 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Sat, 4 May 2024 17:23:14 +0200 Subject: updated README.md for new Makefile --- README.md | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 92f2fe0..1f33d03 100644 --- a/README.md +++ b/README.md @@ -4,10 +4,9 @@ An attempt at building a simple RISCV CPU in verilog. ## Build -* `make all` to synthesize, place and route the design and to generate the bitstream. +* `make all` alias for `make simulate`. +* `make simulate` to run all the testbenches (sim/testbench_*.v). +* `make bitstream` to synthesize, place and route the design and to generate the bitstream. * `make program` to upload the bitstream to the FPGA. * `make flash` to flash the bitsream to the FPGA. -* `make tests` to generate testvec files -* `make simulate` to run the testbench (sim/testbench.v). -* `make wave` to view the simulation in GTKWave. * `make clean` to clean build files. -- cgit v1.2.3