| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-05-21 | restructured project | Flavian Kaufmann | |
| 2024-05-15 | running c program | Flavian Kaufmann | |
| 2024-05-14 | bug fixes | Flavian Kaufmann | |
| 2024-05-13 | refactored fsm output logic | Flavian Kaufmann | |
| 2024-05-13 | refactoring constants | Flavian Kaufmann | |
| 2024-05-13 | async reset | Flavian Kaufmann | |
| 2024-05-13 | refactoring, runs now on fpga | Flavian Kaufmann | |
| 2024-05-12 | refactoring | Flavian Kaufmann | |
| 2024-05-09 | added remaining branch instructions | Flavian Kaufmann | |
| 2024-05-09 | added jalr instruction | Flavian Kaufmann | |
| 2024-05-08 | assemble simple rom | Flavian Kaufmann | |
| 2024-05-07 | alu equal | Flavian Kaufmann | |
| 2024-05-07 | control unit | Flavian Kaufmann | |
| 2024-05-07 | cpu | Flavian Kaufmann | |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
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