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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 17:48:26 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-13 17:48:26 +0200 |
| commit | 9c7d7fd782f70d99120ce6ac45a897606b52c878 (patch) | |
| tree | a6f36fed8ec3e42e08d51afee500190af8194df4 /src/control_unit.v | |
| parent | 05366e24d8b3cfca4b856b1b3740d535cbdf7dd7 (diff) | |
| download | riscv_cpu-9c7d7fd782f70d99120ce6ac45a897606b52c878.tar.gz riscv_cpu-9c7d7fd782f70d99120ce6ac45a897606b52c878.zip | |
refactoring constants
Diffstat (limited to 'src/control_unit.v')
| -rw-r--r-- | src/control_unit.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/control_unit.v b/src/control_unit.v index 0565d5e..494737e 100644 --- a/src/control_unit.v +++ b/src/control_unit.v @@ -14,6 +14,7 @@ module control_unit ( output reg instr_we, output reg rf_we, + output [4:0] ra1, ra2, wa3, output reg [1:0] alu_a_src, output reg [1:0] alu_b_src, @@ -52,6 +53,10 @@ assign opcode = instr[6:0]; assign funct3 = instr[14:12]; assign funct7 = instr[31:25]; +assign ra1 = instr[19:15]; +assign ra2 = instr[24:20]; +assign wa3 = instr[11:7]; + always @ (*) begin case (opcode) |