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| author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-07 21:27:21 +0200 |
|---|---|---|
| committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-07 21:27:21 +0200 |
| commit | 9a357b3ad679751bc7a9ce85adbc303130211226 (patch) | |
| tree | 9898c449a53ff3caa0ae4620a1078c3a8268cbd0 /src/control_unit.v | |
| parent | da9b25591e8b4d1c05a2ac84bb40b5cb5e3a86c5 (diff) | |
| download | riscv_cpu-9a357b3ad679751bc7a9ce85adbc303130211226.tar.gz riscv_cpu-9a357b3ad679751bc7a9ce85adbc303130211226.zip | |
alu equal
Diffstat (limited to 'src/control_unit.v')
| -rw-r--r-- | src/control_unit.v | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/control_unit.v b/src/control_unit.v index 5d18f7a..a0d398a 100644 --- a/src/control_unit.v +++ b/src/control_unit.v @@ -4,6 +4,7 @@ module control_unit ( input [2:0] funct3, input [6:0] funct7, input alu_zero, + input alu_equal, output pc_we, output mem_addr_src, output mem_we, @@ -60,6 +61,12 @@ always @ (*) begin s10_beq: next_state <= s00_fetch; endcase end + +wire branch; +wire pc_update; + +assign pc_we = (alu_zero & branch) | pc_update; + /* always @ (*) begin case(state) |