| Age | Commit message (Expand) | Author |
|---|---|---|
| 2024-05-23 | support for lb, lh, lbu, lhu, sb, sh | Flavian Kaufmann |
| 2024-05-23 | reverted mem size | Flavian Kaufmann |
| 2024-05-23 | mem size | Flavian Kaufmann |
| 2024-05-23 | align | Flavian Kaufmann |
| 2024-05-21 | comments | Flavian Kaufmann |
| 2024-05-21 | restructured project | Flavian Kaufmann |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
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