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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-23 07:04:37 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-23 07:04:37 +0200 |
commit | c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469 (patch) | |
tree | a000085f4ce8d6dec3e90ecc230642eeb77d960f /rtl/src/ram.v | |
parent | ee94c97e4f8208d0c7404887cda16d00f67c6f1f (diff) | |
download | riscv_cpu-c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469.tar.gz riscv_cpu-c6e342f93d1a7fe92d2a7e1b4e488f328e1f4469.zip |
align
Diffstat (limited to 'rtl/src/ram.v')
-rw-r--r-- | rtl/src/ram.v | 23 |
1 files changed, 11 insertions, 12 deletions
diff --git a/rtl/src/ram.v b/rtl/src/ram.v index 7595e89..c0ec231 100644 --- a/rtl/src/ram.v +++ b/rtl/src/ram.v @@ -1,26 +1,25 @@ // ram: // Contains data section of program and is used for stack/heap, etc. -module ram #( - parameter N = 32, - parameter SIZE = 1024 +module ram #( + parameter SIZE = 1024 )( - input clk, - input rstn, - input we, - input [N-1:0] addr, - input [N-1:0] data_write, - output reg [N-1:0] data_read + input clk, + input rstn, + input we, + input [31:0] addr, + input [31:0] wd, + output reg [31:0] rd ); `include "include/log2.vh" //(* RAM_STYLE="BLOCK" *) -reg [N-1:0] mem [0:SIZE-1]; +reg [31:0] mem [0:SIZE-1]; always @(posedge clk) begin - if (we) mem[addr >> 2] <= data_write; - data_read <= mem[addr >> 2]; + if (we) mem[addr >> 2] <= wd; + rd <= mem[addr >> 2]; end endmodule |