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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-21 13:50:28 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-21 13:50:28 +0200
commitcb0be9e2039569ee7d18657e8f675d1f8369b407 (patch)
tree91fa71b3960d1ad5217759371143efbdd833d475 /rtl/src/ram.v
parent98d0dd96611dc2c0e444eaf9410f8adf2924c6b5 (diff)
downloadriscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.tar.gz
riscv_cpu-cb0be9e2039569ee7d18657e8f675d1f8369b407.zip
restructured project
Diffstat (limited to 'rtl/src/ram.v')
-rw-r--r--rtl/src/ram.v23
1 files changed, 23 insertions, 0 deletions
diff --git a/rtl/src/ram.v b/rtl/src/ram.v
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+module ram #(
+ parameter N = 32,
+ parameter SIZE = 1024
+)(
+ input clk,
+ input rstn,
+ input we,
+ input [N-1:0] addr,
+ input [N-1:0] data_write,
+ output reg [N-1:0] data_read
+);
+
+`include "include/log2.vh"
+
+//(* RAM_STYLE="BLOCK" *)
+reg [N-1:0] mem [0:SIZE-1];
+
+always @(posedge clk) begin
+ if (we) mem[addr >> 2] <= data_write;
+ data_read <= mem[addr >> 2];
+end
+
+endmodule