| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-05-08 | waveform example | Flavian Kaufmann | |
| 2024-05-08 | view cpu waveform with make wave | Flavian Kaufmann | |
| 2024-05-08 | updated readme for make rom | Flavian Kaufmann | |
| 2024-05-05 | added info to view waveform with gtkwave to readme | Flavian Kaufmann | |
| 2024-05-04 | renamed some signals | Flavian Kaufmann | |
| 2024-05-04 | updated README.md for new Makefile | Flavian Kaufmann | |
| 2024-05-01 | added make target for testvec generation | Flavian Kaufmann | |
| 2024-04-27 | added README | Flavian Kaufmann | |
 |
index : riscv_cpu.git | |
| Simple RISC-V CPU written in Verilog |
| aboutsummaryrefslogtreecommitdiff |