diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/alu_op_decode.v | 1 | ||||
| -rw-r--r-- | src/control_unit.v | 108 | ||||
| -rw-r--r-- | src/cpu.v | 1 | ||||
| -rw-r--r-- | src/ram.v | 4 | ||||
| -rw-r--r-- | src/register_file.v | 69 | ||||
| -rw-r--r-- | src/rom.v | 4 | ||||
| -rw-r--r-- | src/top.v | 16 |
7 files changed, 172 insertions, 31 deletions
diff --git a/src/alu_op_decode.v b/src/alu_op_decode.v index 64bb94b..8e801c8 100644 --- a/src/alu_op_decode.v +++ b/src/alu_op_decode.v @@ -1,5 +1,6 @@ module alu_op_decode ( input [6:0] opcode, + input [1:0] alu_ctrl, input [2:0] funct3, input [6:0] funct7, output reg [3:0] alu_op diff --git a/src/control_unit.v b/src/control_unit.v index a0d398a..d82db2a 100644 --- a/src/control_unit.v +++ b/src/control_unit.v @@ -6,14 +6,14 @@ module control_unit ( input alu_zero, input alu_equal, output pc_we, - output mem_addr_src, - output mem_we, - output instr_we, - output [1:0] result_src, + output reg mem_addr_src, + output reg mem_we, + output reg instr_we, + output reg [1:0] result_src, output [3:0] alu_op, - output [1:0] alu_a_src, - output [1:0] alu_b_src, - output rf_we + output reg [1:0] alu_a_src, + output reg [1:0] alu_b_src, + output reg rf_we ); parameter s00_fetch = 4'h0, @@ -62,27 +62,89 @@ always @ (*) begin endcase end -wire branch; -wire pc_update; +reg branch; +reg pc_update; +reg [1:0] alu_ctrl; assign pc_we = (alu_zero & branch) | pc_update; -/* + always @ (*) begin - case(state) - s00_fetch: - s01_decode: - s02_mem_addr: - s03_mem_read: - s04_mem_wb: - s05_mem_write: - s06_execute_r: - s07_alu_wb: - s08_execute_i: - s09_jal: - s10_beq: + branch = 1'b0; + pc_update = 1'b0; + mem_we = 1'b0; + rf_we = 1'b0; + instr_we = 1'b0; + case(state) + s00_fetch: begin + mem_addr_src <= 1'b0; + instr_we = 1'b1; + alu_a_src <= 2'b00; + alu_b_src <= 2'b10; + alu_ctrl <= 2'b00; + result_src <= 2'b10; + pc_update = 1'b1; + end + s01_decode: begin + alu_a_src <= 2'b01; + alu_b_src <= 2'b01; + alu_ctrl <= 2'b00; + end + s02_mem_addr: begin + alu_a_src <= 2'b10; + alu_b_src <= 2'b01; + alu_ctrl <= 2'b00; + end + s03_mem_read: begin + result_src <= 2'b00; + mem_addr_src <= 1'b1; + end + s04_mem_wb: begin + result_src <= 2'b01; + rf_we = 1'b1; + end + s05_mem_write: begin + result_src <= 2'b00; + mem_addr_src <= 1'b1; + mem_we = 1'b1; + end + s06_execute_r: begin + alu_a_src <= 2'b10; + alu_b_src <= 2'b00; + alu_ctrl <= 2'b10; + end + s07_alu_wb: begin + result_src <= 2'b00; + rf_we = 1'b1; + end + s08_execute_i: begin + alu_a_src <= 2'b10; + alu_b_src <= 2'b01; + alu_ctrl <= 2'b10; + end + s09_jal: begin + alu_a_src <= 2'b01; + alu_b_src <= 2'b10; + alu_ctrl <= 2'b00; + result_src <= 2'b00; + pc_update = 1'b1; + end + s10_beq: begin + alu_a_src <= 2'b10; + alu_b_src <= 2'b00; + alu_ctrl <= 2'b01; + result_src <= 2'b00; + branch = 1'b1; + end endcase end -*/ + +alu_op_decode aod ( + .opcode(opcode), + .alu_ctrl(alu_ctrl), + .funct3(funct3), + .funct7(funct7), + .alu_op(alu_op) +); endmodule @@ -7,6 +7,7 @@ module cpu ( // Control Unit wire mem_addr_src; +wire mem_we; wire pc_we; wire instr_we; wire rf_we; @@ -21,9 +21,9 @@ always @(posedge clk or posedge rst) begin memory[i] <= 0; end else begin if (we) begin - memory[addr] = data_write; + { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write; end - data_read = memory[addr]; + data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] }; end end diff --git a/src/register_file.v b/src/register_file.v index 5142a69..58ba061 100644 --- a/src/register_file.v +++ b/src/register_file.v @@ -8,9 +8,76 @@ module register_file ( reg [31:0] registers[31:1]; +wire [31:0] reg_x0_zero, + reg_x1_ra, + reg_x2_sp, + reg_x3_gp, + reg_x4_tp, + reg_x5_t0, + reg_x6_t1, + reg_x7_t2, + reg_x8_s0_fp, + reg_x9_s1, + reg_x10_a0, + reg_x11_a1, + reg_x12_a2, + reg_x13_a3, + reg_x14_a4, + reg_x15_a5, + reg_x16_a6, + reg_x17_a7, + reg_x18_s2, + reg_x19_s3, + reg_x20_s4, + reg_x21_s5, + reg_x22_s6, + reg_x23_s7, + reg_x24_s8, + reg_x25_s9, + reg_x26_s10, + reg_x27_s11, + reg_x28_t3, + reg_x29_t4, + reg_x30_t5, + reg_x31_t6; + +assign reg_x0_zero = 32'b0; +assign reg_x1_ra = registers[1]; +assign reg_x2_sp = registers[2]; +assign reg_x3_gp = registers[3]; +assign reg_x4_tp = registers[4]; +assign reg_x5_t0 = registers[5]; +assign reg_x6_t1 = registers[6]; +assign reg_x7_t2 = registers[7]; +assign reg_x8_s0_fp = registers[8]; +assign reg_x9_s1 = registers[9]; +assign reg_x10_a0 = registers[10]; +assign reg_x11_a1 = registers[11]; +assign reg_x12_a2 = registers[12]; +assign reg_x13_a3 = registers[13]; +assign reg_x14_a4 = registers[14]; +assign reg_x15_a5 = registers[15]; +assign reg_x16_a6 = registers[16]; +assign reg_x17_a7 = registers[17]; +assign reg_x18_s2 = registers[18]; +assign reg_x19_s3 = registers[19]; +assign reg_x20_s4 = registers[20]; +assign reg_x21_s5 = registers[21]; +assign reg_x22_s6 = registers[22]; +assign reg_x23_s7 = registers[23]; +assign reg_x24_s8 = registers[24]; +assign reg_x25_s9 = registers[25]; +assign reg_x26_s10 = registers[26]; +assign reg_x27_s11 = registers[27]; +assign reg_x28_t3 = registers[28]; +assign reg_x29_t4 = registers[29]; +assign reg_x30_t5 = registers[30]; +assign reg_x31_t6 = registers[31]; + + integer i; always @(posedge clk or rst) begin - if (rst) begin + if (rst) begin for (i = 1; i < 32; i = i + 1) registers[i] <= 32'b0; end else begin @@ -9,14 +9,14 @@ module rom #( `include "include/log2.vh" -reg [7:0] memory [SIZE-1:0]; +reg [7:0] memory [0:SIZE-1]; initial begin $readmemh("rom/rom.hex", memory, 0, SIZE-1); end always @(posedge clk) begin - data_read = memory[addr]; + data_read <= {memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] }; end @@ -1,9 +1,19 @@ module top ( input clk, - input key, - output [5:0] led + input key + //output [5:0] led ); +wire rst; +assign rst = ~key; + +cpu cpu ( + .clk(clk), + .rst(rst) +); + +/* + reg [5:0] ctr_q; wire [5:0] ctr_d; wire clk_slow; @@ -22,5 +32,5 @@ end assign ctr_d = ctr_q + 6'b1; assign led = ~ctr_q; - +*/ endmodule |