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-rw-r--r--src/io.v6
-rw-r--r--src/top.v2
2 files changed, 5 insertions, 3 deletions
diff --git a/src/io.v b/src/io.v
index f062f31..f53062b 100644
--- a/src/io.v
+++ b/src/io.v
@@ -14,15 +14,17 @@ module io (
`include "include/consts.vh"
-always @ (posedge clk) begin
+always @ (posedge clk or negedge rstn) begin
if (!rstn) begin
io_out <= 32'b0;
end else if (we && addr == 32'h0000_0004) begin
io_out <= wd;
end
+end
+
+always @ (posedge clk) begin
if (addr == 32'h0000_0000) rd <= io_in;
else if (addr == 32'h0000_0004) rd <= io_out;
else rd <= 32'b0;
end
-
endmodule \ No newline at end of file
diff --git a/src/top.v b/src/top.v
index 86f26ce..fc1d9fe 100644
--- a/src/top.v
+++ b/src/top.v
@@ -10,7 +10,7 @@ assign rstn = key;
wire [31:0] io_in;
wire [31:0] io_out;
-clock_divider #(.N(1024 * 1024)) clkdiv (
+clock_divider #(.N(1)) clkdiv (
.clk(clk),
.rstn(rstn),
.clk_div(clk_cpu)