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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-20 12:18:20 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-20 12:18:20 +0200 |
commit | 142510b8325b9ef89bd3e22463f36c3caa2815de (patch) | |
tree | 0668f163046a43e98e8345c6bf96e97a652341c9 /src | |
parent | 407a3ff54a35cbe99ba6ac743376e9b0e9718fc1 (diff) | |
download | riscv_cpu-142510b8325b9ef89bd3e22463f36c3caa2815de.tar.gz riscv_cpu-142510b8325b9ef89bd3e22463f36c3caa2815de.zip |
io
Diffstat (limited to 'src')
-rw-r--r-- | src/io.v | 6 | ||||
-rw-r--r-- | src/top.v | 2 |
2 files changed, 5 insertions, 3 deletions
@@ -14,15 +14,17 @@ module io ( `include "include/consts.vh" -always @ (posedge clk) begin +always @ (posedge clk or negedge rstn) begin if (!rstn) begin io_out <= 32'b0; end else if (we && addr == 32'h0000_0004) begin io_out <= wd; end +end + +always @ (posedge clk) begin if (addr == 32'h0000_0000) rd <= io_in; else if (addr == 32'h0000_0004) rd <= io_out; else rd <= 32'b0; end - endmodule
\ No newline at end of file @@ -10,7 +10,7 @@ assign rstn = key; wire [31:0] io_in; wire [31:0] io_out; -clock_divider #(.N(1024 * 1024)) clkdiv ( +clock_divider #(.N(1)) clkdiv ( .clk(clk), .rstn(rstn), .clk_div(clk_cpu) |