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-rw-r--r--src/instruction_reg.v17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/instruction_reg.v b/src/instruction_reg.v
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+++ b/src/instruction_reg.v
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+module instruction_reg (
+ input clk, rstn, we,
+ input [31:0] pc_in, instr_in,
+ output reg [31:0] pc_buf, instr
+);
+
+always @ (posedge clk) begin
+ if (!rstn) begin
+ pc_buf <= 32'b0;
+ instr <= 32'b0;
+ end else if (we) begin
+ pc_buf <= pc_in;
+ instr <= instr_in;
+ end
+end
+
+endmodule