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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-12 21:27:41 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-12 21:27:41 +0200 |
commit | deb7d0a6fc76d5250c238d479cf97d4755abef01 (patch) | |
tree | 395c266ff4757e83e151d1286d6d2388e63d9a9c /src/instruction_reg.v | |
parent | 008059fbe4e960a10bb4c444013129e0aaa02818 (diff) | |
download | riscv_cpu-deb7d0a6fc76d5250c238d479cf97d4755abef01.tar.gz riscv_cpu-deb7d0a6fc76d5250c238d479cf97d4755abef01.zip |
refactoring
Diffstat (limited to 'src/instruction_reg.v')
-rw-r--r-- | src/instruction_reg.v | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/instruction_reg.v b/src/instruction_reg.v new file mode 100644 index 0000000..f3f456e --- /dev/null +++ b/src/instruction_reg.v @@ -0,0 +1,17 @@ +module instruction_reg ( + input clk, rstn, we, + input [31:0] pc_in, instr_in, + output reg [31:0] pc_buf, instr +); + +always @ (posedge clk) begin + if (!rstn) begin + pc_buf <= 32'b0; + instr <= 32'b0; + end else if (we) begin + pc_buf <= pc_in; + instr <= instr_in; + end +end + +endmodule |