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Diffstat (limited to 'rtl/src/memory_interface.v')
-rw-r--r--rtl/src/memory_interface.v58
1 files changed, 22 insertions, 36 deletions
diff --git a/rtl/src/memory_interface.v b/rtl/src/memory_interface.v
index 01dfa39..055016e 100644
--- a/rtl/src/memory_interface.v
+++ b/rtl/src/memory_interface.v
@@ -2,42 +2,42 @@
// Connects rom, ram and io to memory bus.
module memory_interface (
- input clk,
- input rstn,
+ input clk,
+ input rstn,
- input we,
- input [31:0] addr,
- input [31:0] wd,
+ input we,
+ input [31:0] addr,
+ input [31:0] wd,
output reg [31:0] rd,
- input [31:0] io_in,
- output [31:0] io_out
+ input [31:0] io_in,
+ output [31:0] io_out
);
`include "include/consts.vh"
-reg ram_we;
-reg io_we;
+reg ram_we;
+reg io_we;
wire [31:0] ram_rd, rom_rd;
-reg [31:0] rel_addr;
+reg [31:0] rel_addr;
-ram #(.N(32), .SIZE(1024)) ram(
+ram #(.SIZE(1024)) ram (
.clk(clk),
.rstn(rstn),
.we(ram_we),
.addr(rel_addr),
- .data_read(ram_rd),
- .data_write(wd)
+ .rd(ram_rd),
+ .wd(wd)
);
-rom #(.N(32), .SIZE(1024), .ROM_FILE("../../build/rom.hex")) rom(
+rom #(.SIZE(1024)) rom (
.clk(clk),
.addr(rel_addr),
- .data_read(rom_rd)
+ .rd(rom_rd)
);
-io io(
+io io (
.clk(clk),
.rstn(rstn),
.we(io_we),
@@ -48,33 +48,19 @@ io io(
.io_out(io_out)
);
-
-// 0000 0000 Reserved
-// 0000 FFFF
-//
-// 0001 0000 ROM
-// 000F FFFF
-//
-// 0010 0000 RAM
-// FF0F FFFF
-//
-// FF10 0000 Reserved
-// FFFF FFFF
-
-
always @ (*) begin
- rd = 0;
- rel_addr = 0;
- ram_we = 0;
- io_we = 0;
- if ( addr >= ROM_BEGIN && addr <= ROM_END) begin
+ rd = 0;
+ rel_addr = 0;
+ ram_we = 0;
+ io_we = 0;
+ if (addr >= ROM_BEGIN && addr <= ROM_END) begin
rd = rom_rd;
rel_addr = addr - ROM_BEGIN;
end else if (addr >= RAM_BEGIN && addr <= RAM_END) begin
ram_we = we;
rd = ram_rd;
rel_addr = addr - RAM_BEGIN;
- end else if (addr >= IO_BEGIN && addr <= IO_END) begin
+ end else if (addr >= IO_BEGIN && addr <= IO_END) begin
io_we = we;
rd = io_rd;
rel_addr = addr - IO_BEGIN;