added clock divider

1 files changed, 10 insertions, 2 deletions

diff --git a/src/top.v b/src/top.v
index 6fab4a6..845b17c 100644
--- a/src/top.v
+++ b/src/top.v
@@ -6,13 +6,21 @@ module top (
 
 reg [5:0] ctr_q;
 wire [5:0] ctr_d;
+wire clk_slow;
+assign reset = ~key;
 
-always @(posedge clk) begin
+clock_divider #(.N(10000000)) clk_div (
+  .clk(clk),
+  .clk_out(clk_slow),
+  .reset(reset)
+);
+
+always @(posedge clk_slow) begin
 	if (key) ctr_q <= ctr_d;
 	else ctr_q <= 6'b0;
 end
 
 assign ctr_d = ctr_q + 6'b1;
-assign led = ctr_q;
+assign led = ~ctr_q;
 
 endmodule