From 08d6eea4fc23e7f569bbfd883f0dc049272a4b47 Mon Sep 17 00:00:00 2001 From: Flavian Kaufmann Date: Sat, 27 Apr 2024 14:52:08 +0200 Subject: added clock divider --- src/top.v | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'src/top.v') diff --git a/src/top.v b/src/top.v index 6fab4a6..845b17c 100644 --- a/src/top.v +++ b/src/top.v @@ -6,13 +6,21 @@ module top ( reg [5:0] ctr_q; wire [5:0] ctr_d; +wire clk_slow; +assign reset = ~key; -always @(posedge clk) begin +clock_divider #(.N(10000000)) clk_div ( + .clk(clk), + .clk_out(clk_slow), + .reset(reset) +); + +always @(posedge clk_slow) begin if (key) ctr_q <= ctr_d; else ctr_q <= 6'b0; end assign ctr_d = ctr_q + 6'b1; -assign led = ctr_q; +assign led = ~ctr_q; endmodule -- cgit v1.2.3