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author | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-15 09:27:51 +0200 |
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committer | Flavian Kaufmann <flavian@flaviankaufmann.ch> | 2024-05-15 09:27:51 +0200 |
commit | def3f62f7f8d6b5bd4b15500c7d11935540e81da (patch) | |
tree | b4fb8037a58ae498ba6f9c92ab246b0fba7eded7 /src/ram.v | |
parent | 9e76b9001c37ab2da2e99c922406b991bd0e53af (diff) | |
download | riscv_cpu-def3f62f7f8d6b5bd4b15500c7d11935540e81da.tar.gz riscv_cpu-def3f62f7f8d6b5bd4b15500c7d11935540e81da.zip |
fixed relative memory addressing bug
Diffstat (limited to 'src/ram.v')
-rw-r--r-- | src/ram.v | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -5,7 +5,7 @@ module ram #( input clk, input rstn, input we, - input [log2(SIZE/4)-1:0] addr, + input [N-1:0] addr, input [N-1:0] data_write, output reg [N-1:0] data_read ); @@ -13,7 +13,7 @@ module ram #( `include "include/log2.vh" //(* RAM_STYLE="BLOCK" *) -reg [N-1:0] mem [SIZE-1:0]; +reg [N-1:0] mem [0:SIZE-1]; always @(posedge clk) begin if (we) mem[addr >> 2] <= data_write; |