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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-08 10:55:45 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-08 10:55:45 +0200
commitaa005bc8b667668eb43c0ae62e00aefd1c3c1af5 (patch)
treea491b20a750cf0dac413aa10deb2ead3b6266fc3 /src/ram.v
parent80fee7a2db703f029989c40e823c2ccdeb078fca (diff)
downloadriscv_cpu-aa005bc8b667668eb43c0ae62e00aefd1c3c1af5.tar.gz
riscv_cpu-aa005bc8b667668eb43c0ae62e00aefd1c3c1af5.zip
assemble simple rom
Diffstat (limited to 'src/ram.v')
-rw-r--r--src/ram.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/ram.v b/src/ram.v
index f92c66f..92b14a2 100644
--- a/src/ram.v
+++ b/src/ram.v
@@ -21,9 +21,9 @@ always @(posedge clk or posedge rst) begin
memory[i] <= 0;
end else begin
if (we) begin
- memory[addr] = data_write;
+ { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] } = data_write;
end
- data_read = memory[addr];
+ data_read = { memory[addr + 3], memory[addr + 2], memory[addr + 1], memory[addr + 0] };
end
end