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authorFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-05 15:01:46 +0200
committerFlavian Kaufmann <flavian@flaviankaufmann.ch>2024-05-05 15:01:46 +0200
commit90a684ff92f68ec818349d1df626fcb06e8de2a1 (patch)
treed795baf38d56520f807a7f54252ce51b71061f45 /src/ram.v
parent5392b3d94038963a7121f391ad1b5075a5e32b8e (diff)
downloadriscv_cpu-90a684ff92f68ec818349d1df626fcb06e8de2a1.tar.gz
riscv_cpu-90a684ff92f68ec818349d1df626fcb06e8de2a1.zip
initialize rom to rom/rom.hex
Diffstat (limited to 'src/ram.v')
-rw-r--r--src/ram.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/ram.v b/src/ram.v
index b7e4c80..f92c66f 100644
--- a/src/ram.v
+++ b/src/ram.v
@@ -12,18 +12,18 @@ module ram #(
`include "include/log2.vh"
-reg [8:0] ram_block [SIZE-1:0];
+reg [8:0] memory [SIZE-1:0];
integer i;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (i = 0; i < SIZE; i = i + 1)
- ram_block[i] <= 0;
+ memory[i] <= 0;
end else begin
if (we) begin
- ram_block[addr] = data_write;
+ memory[addr] = data_write;
end
- data_read = ram_block[addr];
+ data_read = memory[addr];
end
end